1. Field of the Invention
This invention relates in general to electronic circuits integrated on a semiconductor substrate. More particularly, this invention relates to circuits used to create reference biasing voltages for a common plate of a cell capacitor of a memory storage cell of a dynamic random access memory.
2. Description of the Related Art
FIG. 1 illustrates the general structure of an array of memory storage cells CELL 0, CELL 1, CELL 2, and CELL 3 of a dynamic random access memory (DRAM). Each cell CELL 0, CELL 1, CELL 2, and CELL 3 is formed of a single metal oxide semiconductor (MOS) transistor N.sub.P and a cell capacitor C.sub.C. The drain of the pass transistor N.sub.P is connected to a top plate of the cell capacitor C.sub.C. The source of the pass transistor N.sub.P is connected to one of the bit-lines BL0, BL0B, BL1, BL1B. The gate of the pass transistor N.sub.P is connected to one of the word-lines WL0 and WL1. The commonly connected plates of all the cell capacitors C.sub.C is connected to a cell plate biasing voltage source V.sub.P. The voltage level of the cell plate biasing voltage source V.sub.P is designed to be an intermediate value between the voltage level of the power supply voltage source V.sub.DD and the ground reference point GND. The voltage level of the plate biasing voltage source V.sub.P is set such that the voltage developed across the cell capacitors is reduced.
When a cell is to have a bit of digital data written to or retrieved from a cell, one of the word-lines WL0 or WL1 is brought to a voltage level greater than the threshold voltage V.sub.TH of the pass transistor N.sub.P plus the voltage level present on either the drain or source of the pass transistor. The bit-lines BL0, BL0B, BL1, BL1B are pre-charged to a voltage level that is one half the value of the voltage level of the power supply voltage source V.sub.DD, if the memory cell is to have the bit of digital data retrieved from it. If the memory cell contains a high logic level (1), the voltage level of the top plate of the cell capacitor is approximately the voltage level of the power supply voltage source V.sub.DD. Conversely, if the memory cells contains a low logic level (0), the voltage level at the plate of the cell capacitor is approximately the voltage level of the ground reference point GND. When the pass transistor is activated, a charge flows to or flows from the top plate of the cell capacitor C.sub.C. The sense amplifier SA0 or SA1 senses and amplifies this charge flow and forces the bit-lines BL0, BL0B, BL1, BL1B to the appropriate voltage level (V.sub.DD or GND) dependent on the logic level stored at the top plate of the cell capacitance.
For writing a bit of digital data to the memory cell, the bit-lines BL0, BL0B, BL1, BL1B are pre-charged appropriately to the voltage level of the desired logic level (V.sub.DD or GND).
The appropriate word-line WL0 or WL1 is activated to turn on the pass transistor N.sub.P. The voltage present on the appropriate bit-line BL1, BL1B, BL2, or BL2B flows to charge or discharge the cell capacitor.
Refer now to FIG. 2 for a discussion of a typical cell plate reference voltage generator of the prior art. The cell plate reference voltage generator includes a biasing circuit composed of MOS transistors N10, P10, N11 and P11 and an output buffer circuit composed of MOS transistors N12 and P12. The biasing circuit is designed to provide adequate bias to the output circuit such that the cell plate reference voltage generator provides a desired cell plate reference voltage V.sub.P. In the circuit as shown, the ratio of the sizes of MOS transistors P10 and N11 is used to determine the right level of the cell plate reference voltage V.sub.P while the ratio of the sizes of MOS transistor N10 and P11 relative to those of MOS transistors P12 and N12 determines the static current of the cell plate reference voltage generator provided by MOS transistors N12 and P12. If this static current is high, the cell plate reference voltage generator has low output impedance or high drive ability. Alternately, cell plate reference voltage generator has high output impedance or low drive ability, if the static current is low. To limit the stand-by power consumption of the DRAM chip the static current provided by the cell plate reference voltage generator must be kept low.
However, the low static current characteristic of the conventional cell plate reference voltage generator can create a severe problem during memory access. Referring to FIG. 1 and FIG. 2, during memory access all the memory cells connected to selected word-lines are enabled and may be accessed by corresponding bit-lines. That is, the current in the bit-lines may charge or discharge the storage capacitors of the selected memory cells when the corresponding access transistors are turned on as described above. Therefore, current surges flowing into and from the storage capacitors can occur in the period of memory write and read cycles. Voltage noise in the cell plate reference voltage V.sub.P will occur as a result of the cell plate reference voltage generator having less drive ability and not being able to provide adequate current to these storage capacitors.
This induced voltage noise may be lower or higher than the normal level of the cell plate reference voltage V.sub.P. It is known that memory cells that are not being access may be disturbed due to noise on their common plates of the cell capacitor C.sub.C that brings the cell plate reference voltage V.sub.P lower than the normal level. For any memory cell not being accessed, the gate of its pass transistor N.sub.P is connected to a grounded word-line, and, therefore, the pass transistor N.sub.P is turned off. Basically, negative voltage noise on the common plate of the cell capacitor can not charge or discharge the cell capacitor C.sub.C as long as the access transistor is kept off. As a result, the voltage on the storage node D.sub.X of the storage capacitor moves down with this noise that lowers the voltage level of the cell plate reference voltage generator for the same amount. Usually, the pass transistors N.sub.P in DRAMS are N-type MOS transistors. If a low voltage or zero voltage is stored in the memory cell not being accessed and the magnitude of the noise that lowers the voltage level of the cell plate reference voltage generator is greater than the threshold voltage V.sub.TH of its pass transistor N.sub.P, the pass transistor N.sub.P will turn on and introduce current from the connected bit-lines BL0, BL0B, BL1, BL1B to flow through the cell capacitor C.sub.C. Thus the memory cell is disturbed by the negative noise that lowers the voltage level of the cell plate reference voltage generator. The sub-threshold current of the pass transistor N.sub.P also increases even though the negative noise that lowers the voltage level of the cell plate reference voltage generator is not sufficient to completely turn on the pass transistor N.sub.P.
Two conventional techniques may be used to reduce disturbance effects caused by noise that lowers the voltage level of the cell plate reference voltage generator. The first technique is to implement pass transistors having a high threshold voltage V.sub.TH to increase noise margin. However, a pass transistor with a high threshold voltage level V.sub.TH will slow down memory access. The alternative is to apply a negative voltage to the unselected word-lines to reverse-bias these pass transistors N.sub.P, but that requires extra control circuitry in each decoder and driver connected to the word lines and consequently requires more area and consumes more power.
An example of the effect of the noise present at the cell plate reference voltage generation circuit is shown in FIG. 3. In this example the memory cell CELL 1 of FIG. 1 has a high logic level (1) present on the top plate D1 of the cell capacitor C.sub.C and the memory cell CELL 0 has a low logic level (0) present on the cell capacitor. The voltage level present at the junction D1 of the top plate of the cell capacitor C.sub.C and the drain of the pass transistor N.sub.P of the memory cell CELL 1 is at the voltage level of the power supply voltage source V.sub.DD. The voltage level present at the junction D0 of the top plate of the cell capacitor C.sub.C and the drain of the pass transistor N.sub.P of the memory cell CELL 0 is at approximately the voltage level of the ground reference point GND. The bit-lines BL0 and BL0B are brought to a voltage level that is approximately one-half the voltage level of the power supply voltage source (V.sub.DD /2).
The word-line WL0 is brought to a voltage level such that the pass transistor N.sub.P of the memory cell CELL 1 is turned on at time T.sub.0 and the charge present on the top plate D1 of the cell capacitor C.sub.C of the memory cell CELL 1 flows to the bit-line BL0. The voltage levels of the top plate D1 of the cell capacitor C.sub.C of the memory cell CELL 1 and the bit-line BL0 become equal.
During the flow of charge from the top plate D1 of the cell capacitor C.sub.C of the memory cell CELL 1, the voltage level of the cell plate reference voltage V.sub.P decreases by the amount .DELTA.V.sub.P. This is a result of the lack of the output butter of FIG. 2 being able to provide sufficient current. Since the top plate D0 of the cell capacitor C.sub.C of memory cell CELL 0 is not selected, its voltage will also decline by the amount .DELTA.V.sub.DD.
At the time T.sub.1, the sense amplifier enable signal SAE changes from the low logic level (0) to the high logic level (1), thus activating the sense amplifier SA0. The difference between the bit-lines BL0 and BL0B is sensed and amplified and the bit-line BL0 and the top plate D1 of cell capacitor C.sub.C of the memory cell CELL 0 are forced at time T.sub.2 to the voltage level of the power supply voltage source V.sub.DD. At this same time T.sub.2, the bit-line BL0B is forced to the voltage level approaching that of the ground reference point GND.
The physical structure of the distribution paths of the bit-lines BL0 and BL0B and the cell plate reference voltage generator V.sub.P cause parasitic capacitances to be present between these distribution paths. Thus, when the sense amplifier enable signal SAE is activated at time T.sub.1, the bit-line BL0 is forced to the voltage level of the power supply voltage source V.sub.DD, and the bit-line BL0B is forced to the voltage level approaching the ground reference point, the voltage level of the cell plate reference voltage generator V.sub.P will again vary.
If, as described above, the voltage present at the top plate D0 of the cell capacitor C.sub.C of the memory cell CELL 0 is sufficiently large, the pass transistor N.sub.P of the memory cell CELL 0 will conduct sufficiently to cause the voltage level at the top plate D0 of the cell capacitor C.sub.C of the memory cell CELL 0 to change by the amount .DELTA.V.sub.DD2. This voltage variation .DELTA.V.sub.DD2 may be sufficient to cause errors in the digital data retained in the memory.
A third solution to the noise that lowers the voltage level of the cell plate reference voltage generator is described in U.S. Pat. No. 5,734,603 (Tai) as shown in FIG. 4.
The cell plate noise-reducing circuit of Tai includes a sampling circuit, a comparator and a charge device P43. The sampling circuit maintains a sample voltage at node SVP, which is identical to the cell plate reference voltage V.sub.P when there is no memory access in the DRAM. The comparator is a controllable device that receives the sample voltage at node SVP and the noisy cell plate reference voltage V.sub.P and generates a difference voltage at node A corresponding to the cell plate noise. The difference voltage at node A controls charged device P43. When the difference voltage at node A represents the situation of negative noise on the cell plate reference voltage, the charge device P43 provides a temporarily large current to the cell plate reference voltage V.sub.P.
The sampling circuit includes capacitor CAP40 and PMOS transistor switch P42. PMOS transistor switch P42 is connected between capacitor CAP40 and the cell plate reference voltage V.sub.P and is controlled by enable signal. The comparator includes PMOS transistors P40 and P41 that provide current mirror loads for differential pair NMOS transistors N40 and N41. NMOS transistor N42 is a controlled transistor that enables or disables comparator. The PMOS transistor P43 is a large-scale transistor that is connected to the power supply voltage source V.sub.DD to provide a large current to V.sub.P.
Cell plate noise occurs when there is a memory access, and therefore, the cell plate noise is predictable. The enable signal ENABLE is in low logic level (0) if there is no memory access. However, the enable signal ENABLE is in high logic level (1) during memory access. When enable signal ENABLE is in low logic level (0), the comparator is disabled and will not contribute static current in the DRAM. However, enable signal ENABLE turns on PMOS transistor P42, allowing the sample voltage at node SVP to be identical to the cell plate reference voltage V.sub.P. When there is memory access, the enable signal ENABLE then switches to the high logic level (1), enabling the comparator while disabling PMOS transistor P42. As a result, the normal level of the cell plate reference voltage V.sub.P is held at node SVP. When cell plate noise lowers the voltage level of the cell plate reference voltage V.sub.P because of the memory access, the noisy cell plate reference voltage V.sub.P is compared with the sample voltage at node SVP. A negative noise in the cell plate reference voltage V.sub.P is amplified in contrast to the sample voltage at node SVP. The amplified negative signal at node A is applied to the gate of PMOS transistor P43 and the PMOS transistor P43 is turned on to provide a large current to the common plates of the cell capacitors C.sub.C for pulling up the voltage at this node. The PMOS transistor P43 provides a negative feedback path for the comparator thus suppressing the noise level at the cell plate reference voltage V.sub.P.
U.S. Pat. No. 4,769,784 (Doluca et al.) describes a plate capacitor bias generator. The capacitor-plate bias generator produces a voltage on the common capacitor plate node of the DRAM cell capacitor. The voltage consists of a constant voltage plus the sense-level voltage. Consequently, the capacitor-plate node tracks any variations in the sense-level voltage. The constant voltage is 3 times the bandgap voltage of silicon. The circuit includes a reference-voltage source which produces the sum of the sense-level voltage and the bandgap voltage, and a feedback control circuit for enabling either a charge pump or a charge bleeder to regulate the capacitor-plate voltage at a level above the circuit supply voltage.
U.S. Pat. No. 5,255,232 (Foss et al.) teaches a method for pre-charging a memory cell bit storage capacitor. The storage capacitor reference plate is driven from a high impedance voltage divider, minimizing the effects of voltage supply noise. This prevents the voltage supply noise from coupling to storage capacitor and turning on the associated capacitor access transistor.